EE542 Digital Systems Verification and Testing

Fall 2005

Instructor: Ilker Hamzaoglu
Office: MDBF 1037

Description: This course introduces the problems of design verification and testing. It then covers the digital systems testing process, various fault models, automatic test pattern generation (ATPG), fault simulation, memory test, design for testability, built-in self-test, SoC test structures. After that, the course covers the design verification process, simulation-based verification, emulation-based verification, and formal verification. Finally, it covers ATPG-based verification techniques. In this course, students will also gain practical testing and verification experience by using several CAD tools from Synopsys (DFT Compiler, TetraMax ATPG, Formality) and Mentor Graphics (Modelsim), and by writing a small scale CAD software implementing a verification or testing algorithm.

Course Info

Textbook

• Essentials of Electronic Testing , Michael J. Bushnell, Vishwani D. Agrawal, Kluwer Academic Publishers, 2000

Reference Books

• Digital Systems Testing and Testable Design , Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman, IEEE, 1994
• Design-For-Test for Digital ICs and Embedded Core Systems , Alfred Crouch, Pearson Education, 1999
• Functional Verification of HDL Models , Janick Bergeron, Kluwer Academic Publishers, 2nd Edition, 2003
• System-on-a-Chip Verification: Methodology and Techniques
  Prakash Rashinkar, Peter Paterson, Leena Singh, Kluwer Academic Publishers, 2001
• Introduction to Formal Hardware Verification , Thomas Kropf, Springer-Verlag,1999

Reference Materials

• Mentor Graphics FastScan Presentation
• Arm11 Memory Bist Controller TRM
• IEEE P1500 Presentation
• IEEE P1500 Paper
• SwitchCore Functional Verification
• HP Microprocessor Verification
• Formal Verification Presentation by Tom Henzinger
• Binary_Decision_Diagrams

Lecture Notes (Accessible only from Sabanci University Intranet)

• Instructor's Slides
• Verification vs Testing
• Formal_Verification
• Checking_Experiment_Example
• Textbook (Bushnell and Agrawal) Slides
• Introduction
• Fault_Modeling
• Logic_and_Fault_Simulation
• Testability_Measures
• Combinational_Circuit_ATPG
• Sequential_Circuit_ATPG
• Design_For_Testability (DFT)
• Built_in_Self_Test (BIST)
• JTAG_Boundary_Scan
• Memory_Test
• Memory_BIST
• Delay_Test
• IDDQ_Testing
• Fault_Diagnosis
• System_Test
• UIUC ECE443 Lecture Notes by Rudnick

Final_Exam_Sample_Questions

Project

• Hitec_Proofs User's Manual
• Hitec_Proofs Sun Solaris Binary
• ISCAS85 Benchmarks

Links

• IGATE Research Group at UIUC