EE542 Digital Systems
Verification and Testing
Fall 2005
Instructor: Ilker Hamzaoglu
Office: MDBF 1037
Description: This course
introduces the problems of design verification and testing. It then
covers the digital systems testing process, various fault models,
automatic test pattern generation (ATPG), fault simulation, memory test, design for testability,
built-in self-test, SoC
test structures. After that, the course
covers the design verification process, simulation-based verification, emulation-based verification, and formal verification. Finally, it covers ATPG-based verification techniques. In this course, students
will also gain practical testing and verification
experience by using several CAD tools from Synopsys
(DFT Compiler, TetraMax
ATPG, Formality) and Mentor Graphics (Modelsim), and by writing
a small scale CAD software implementing a verification or testing algorithm.
Textbook
Reference Books
Reference Materials
Lecture Notes (Accessible only from Sabanci University Intranet)
Links