EL 401 VLSI SYSTEM DESIGN I

Fall 2008

Instructor: Ilker Hamzaoglu
Office: MDBF 1037

Teaching Assitant: Mert Cetin
Office: MDBF 1042

Description: This course discusses fundamentals of digital CMOS VLSI design, and it covers full-custom and standard cell based digital VLSI circuit design. Students will learn the design flow for both design styles and they will become familiar with the issues involved in the individual design steps. They will also gain practical design experience by using several CAD tools (Synopsys Design Compiler, Mentor Graphics Modelsim, Cadence Virtuoso and Silicon Ensemble) to design, implement and verify a VLSI circuit.

Textbooks

• Digital Integrated Circuits, Jan M. Rabaey, Anantha P. Chandrakasan, Borivoje Nikolic, Prentice Hall, 2nd Edition
• Application-Specific Integrated Circuits, Michael J. S. Smith, Addison Wesley, 1997 (Supplementary Materials)

Reference Books

• Principles of CMOS VLSI Design: A Systems Perspective, Neil H. West, Kamran Eshraghian, 2nd Edition
• Advanced ASIC Chip Synthesis, Himanshu Bhatnagar,  Kluwer Academic Publishers, 2nd Edition
• Algorithms for VLSI Physical Design Automation, Naveed A. Sherwani, Kluwer Academic Publishers, Third Edition
• Timing Verification of ASICs, Farzad Nekoogar, Prentice Hall
• Closing the Gap between ASIC & Custom, David Chinnery, Kurt Keutzer, Kluwer Academic Publishers

Reference Materials

· Transistor_History

· VLSI_Education

· Cadence Tutorial

· AMS 0.35µ Process Parameters

· AMS 0.35µ Design Rules

· Dynamic_CMOS_Logic

· Beat_the_Heat

· Low_Power_CMOS_Digital_Design

· Multi-Asynchronous_Clock_Designs

· Samsung Sram

· Intel Flash Memory

· Micron Sdram

· VS UMC 0.18µ Cell Library

· AMS 0.35µ Cell Library

· AMS 0.35µ I/O Pad Library

· The_Art_of_Standard_Cell_Library_Design

· Logic Synthesis

· Synopsys Synthesis Checklist

· 8-bit Adder Synthesis Results

· VLSI_Circuits_Partitioning

· SiliconEnsemble_Tutorial_Slides

· SiliconEnsemble_Tutorial_Paper

· SiliconEnsemble_Delay_Calculation

· Avant! Hierarchical Layout Example

· STA_Presentation

· Asic_Design_Process

Lecture Notes (Accessible only from Sabanci University Intranet)

· Introduction

· VLSI_Design_Methods

· Manufacturing Process

· CMOS_Capacitances_Resistances

· CMOS_Delay_Estimation

· CMOS_Circuit_Layout_Design

· Low_Power_CMOS_Design

· Arithmetic_Circuits_Design

· Timing_in_VLSI_Circuits

· Semiconductor_Memories

· Standard_Cell_Libraries

· Logic_Synthesis_Synopsys_Dc_Pc

· Design_Verification

· Physical_Design_Partitioning

· Floorplanning_Power_Distribution

· IO_Pads_Packaging

· Placement_Routing

· Layout_Timing_Verification

Lab Assignments

· Lab 1 (Full-custom datapath design in AMS 0.35µ technology)

o Manchester Carry-Skip Adder

· Lab 2 (Verilog RTL design and Synthesis to AMS 0.35µ and UMC 0.18µ cell libraries)

· Lab 3 (Place and Route with SiliconEnsemble and Timing Simulation)

Exams

· Midterm_Exam_Fall03

· Final_Exam_Fall03

· Midterm_Exam_Fall04

· Final_Exam_Fall04