CS 303 Logic & Digital System Design

Fall Term 2019
Computer Science
Sabancı University

Announcements

  • September 16: Check days, time, and location
  • September 16 : Check the rules and regulations below (Important!!)
  • September 16: Check the schedule
  • September 16: Check the syllabus
  • September 16: No recitation first week
  • September 16: No lab first week
  • September 16: Check SUCourse for announcements. There will be no further announcements here.

Textbook

M. Morris Mano and Michael D. Ciletti. Digital Design: With an Introduction to the Verilog HDL. Fifth Edition, Prentice Hall, 2013, ISBN-13 978-0-273-76452-6.

Recommended Resources

M. Morris Mano and Michael D. Ciletti. Digital Design. Fourth Edition, Prentice Hall, 2007, ISBN 978-13-234043-4.

Morris M. Mano and Charles R. Kime. Logic and Computer Design Fundamentals. Prentice Hall, 2004.

Time & Place

  • Lecture:

·         Section A (10507): Tuesday 12:40 – 14:30, FENS G077

·         Section A (10507): Thursday 15:40 – 16:30, FENS G077

·         Section B (10508): Thursday 10:40 – 11:30, FASS G062

·         Section B (10508): Friday 12:40 – 14:30, FENS G077

  • Recitation:

·         Section A (10519): Friday 08:40 – 10:30, FASS G062

·         Section B (10520):Thursday 17:40 – 19:30, FENS G077

  • Lab Sections:      

·         Section A (10509): Monday 14:40 – 16:30, FENS 1033

·         Section B (10510): Tuesday 08:40 – 10:30, FENS 1033

·         Section C (10511): Wednesday 10:40 – 12:30, FENS 1033

·         Section D (10512): Tuesday 10:40 – 12:30, FENS 1033

·         Section E (10513): Monday 11:40 – 13:30, FENS 1033

·         Section F (10514): Friday 17:40 – 19:30, FENS 1033

·         Section G (10515): Wednesday 17:40 – 19:30, FENS 1033

·         Section H (10516): Tuesday 15:40 – 17:30, FENS 1033

·         Section I (10517): Wednesday 14:40 – 16:30, FENS 1033

·         Section J (10518): Tuesday 17:40 – 19:30, FENS 1033

 

  • Teaching Assistants
    • Ahmet Can Mert - FENS 2014
    • Atýl Utku Ay - FENS 2014
    • Þeyma Selcan Maðara
    • Mehmet Bora Özdemir
    • Berke Ayrancýoðlu
    • Seyedpayam Seyedkazemi

 

  • Office Hours (Incomplete)

 

 

Monday

Tuesday

Wednesday

Thursday

Friday

08:40 - 09:30

 

 

 

 

Erkay Savas  

 

09:40 – 10:30

 

Erkay Savas  

10:40 – 11:30

 

11:40 - 12:30

 

 

 

12:40 – 13:30

 

13:40 – 14:30

 

 

14:40 – 15:30

 

 

 

 

 

15:40 – 16:30

 

 

 

 

16:40 – 17:30

 

 

 

 

17:40 – 18:30

 

 

 

 

 

 

18:40 – 19:30

 

 

 

 

19:40 – 20:30

 

 

 

 

 

 

 

Motivation

This is a 4-credit, introductory course on logic and digital system design.

Topics

  • Number Systems & Arithmetic
  • Boolean Algebra & Logic Operations
  • Gate-Level Minimization
  • Analysis & Design of Combinational Logic Circuits
  • Analysis & Design of Synchronous Sequential Logic Circuits
  • Registers & Counters
  • Memory & Design with Programmable Logic
  • Design with Algorithmic State Machines (ASM)

Lab Assignments

  • There will be 4-5 lab assignments.
  • It is essential to attend the lab session you are registered in and demonstrate your work during the session.

Examinations

·         There are two midterms and a final examination

Class Notes

  • Class notes will be posted on SuCourse under Classnotes. However, you are required to attend the lectures to get all the material covered during the lectures.

Tentative grading

  • Midterms: 35 % (20 % + 15 % or vice versa)
  • Final: 35 %
  • Lab Assignments: 15 %
  • Short Homework: 5 % 
  • Term Project: 10 %

Important Dates

  • First midterm: TBA
  • Second midterm:  December
  • Final: As scheduled by registrar

Class Project for Fall 2019

  • Project Requirements
  • Proposal Due Date: TBA.
  • Electronic Copy Due Date: TBA

Rules & Regulations

·        It is obligatory to attend all the lab sessions. Missing one lab session will result in you not being able to get any credit from the lab assignments (15% in total)

·        There is no partial credit for the term project. The students are required to fulfill all the project steps as described, and submit & demonstrate a working version.

·        It is essential to attend all the lectures. The attendance will be collected at times. Failing to be in attendance lists three times MAY result in one letter down in your final grade.

Prerequisites

This class is open to all undergraduate students.

Dr. Erkay Savaþ