EL 310 Hardware Description
Languages
Fall 2003
Sabanci University
Announcements
- September 23:
Days, time, and room: Tuesday - 08:40-09:30 - G035, Friday 08:40-10:30 -
L045
- September 23:
In order to view or print the PDF files, you need Adobe
Acrobat Reader.
Make sure that you install Acrobat 5.0 in your computer; otherwise, you
may not be able
to view or print the documents.
- October 7:
First Lab session. A lecture on the development environment by the TA.
- October 14:
First Lab assignment. Due October 21, 2003 during lab
hours.
- November 2:
Second Lab assignment, Due November 4, 2003, see the WebCT .
Textbook
Sudhakar Yalamanchili. Introductory
VHDL: From Simulation to Synthesis, Prentice Hall, Inc. 2001. ISBN:
0-13-080982-9
Other Resources
- Jayaram
Bhasker. A VHDL Primer. Prentice Hall, 1999.
- Mark Zwolinski, Digital System
Design with VHDL, Prentice Hall, 2000.
- Weng
Fook Lee. VHDL Coding and Logic Synthesis with Synopys®. Academic
Press, 2000.
- Jayaram
Bhasker. Verilog HDL Synthesis: A Practical Primer. Star Galaxy
Publishing, 1998
- Weng
Fook Lee. Verilog Coding for Logic Synthesis. Wiley Interscience,
2003.
.
Time & Place
- Tuesday: 08:40 -
09:30, G035
- Friday: 08:40 -
10:30, L045
- Lab Session: Tuesday:
12:40 – 14:30, FENS 1062
Office Hours
Thursday 09:40 am - 11:30 (or by
appointment)
Teaching Assistant
Kazim Yumbul
Motivation
This is a 4-credit, introductory course on the use of VHDL
for the design, synthesis, modeling, and testing of VLSI devices. VHDL is an
IEEE standard that is used by engineers to efficiently design and analyze
complex digital designs. The other most commonly used HDL, Verilog, is
also introduced within the scope of this course.
Topics
- Introduction
- Digital Design Overview
- Modeling Digital Systems
- Simulation versus Synthesis
- Basic Language Concepts: Simulation
- Basic Language Concepts: Synthesis
- Modeling Behavior: Simulation
- Modeling Behavior: Synthesis
- Modeling Structure
- Sub-Programs and Libraries
- Basic I/O
- Programming Mechanics
- Identifiers, Data Types, and Operators
- An Introduction to Verilog
- Design and Synthesis with Verilog
Lab &Homework Assignments
Homework assignments and their solutions will be posted
here. Handwritten assignments are not acceptable. The source and object codes
must be submitted as electronic copy. Others will be submitted as hardcopy.
Submission must be done at the beginning of a lecture.
Course Materials
Course materials such as presentation slides and
handouts will be posted here
Tentative grading
- Midterm: 25 %
- Final: 35 %
- Lab & HW
Assignments 20 %
- Project: 20 %
Important Dates
Important dates such as exams and homework due dates will be posted
here.
Examinations
Solutions for exams will be posted here.
Class Projects & Assignments
- Lab &
Homework assignments: There
will be around six laboratory and/or homework assignments. You will be
required to use VHDL for most of the lab assignments and Verilog for the
rest.
- EL 310 class
projects: In addition to lab and homework assignments, the students
are required to work on a big development project. Students may propose
a project even though assigning class projects is normally the
responsibility of the instructor.
Students
may work in groups. Student’s proposals are subject to instructor’s approval.
It is essential for students to meet time schedule of the projects. Project
groups must provide a demonstration of their work. During the demonstration,
all the project members must be present.
Resources and Pointers
Prerequisites
CS 303 (Minimum Grade: D)
Dr. Erkay Savas
|